View XC3000_8610079.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 1 ? copyright 2010 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tr ademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. features ? configuration one-time programmable (otp) read-only memory designed to store configuration bitstreams of xilinx fpga devices ? on-chip address counter, incremented by each rising edge on the clock input ? simple interface to the fpga requires only one user i/o pin ? cascadable for storing longer or multiple bitstreams ? programmable reset polarity (active high or active low) for compatibility with different fpga solutions ? low-power cmos eprom process ? available in 5v version only ? programming support by leading programmer manufacturers. ? design support using the xilinx alliance and foundation series software packages description the xc1700e qpro? family of configuration proms provide an easy-to-use, cost-e ffective method for storing xilinx fpga configuration bitstreams. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the fpga d in pin. the fpga generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when the fpga is in slave serial mode, the prom and the fpga must both be clocked by an incoming signal. multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family. for device programming, either the xilinx alliance? or the foundation? series development systems compiles the fpga design file into a standard hex format which is then transferred to most commercial prom programmers. 11 qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 product specification x-ref target - figure 1 figure 1: simplified block diagram (doe s not show programming circuit) eprom cell matrix address counter ce data oe output clk v cc v pp gnd ds670_01_112910 tc reset/oe or oe/reset ceo
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 2 pin description data data output, 3-stated when either ce or oe are inactive. during programming, the data pin is i/o. note: oe can be programmed to be either active high or active low. clk each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/oe when high, this input holds the address counter reset and 3-states the data output. the polarity of this input pin is programmable as either reset/oe or oe/reset . to avoid confusion, this docum ent describes the pin as reset/oe , although the opposite polarity is possible on all devices. when reset is active, the address counter is held at zero, and the data output is put in a high-impedance st ate. the polarity of this input is prog rammable. the default is active high reset, but the preferred optio n is active low reset , because it can be driven by the fpga?s init pin. the polarity of this pin is controlled in the programmer interface. th is input pin is easily invert ed using the xilinx hw-130 programmer software. third-party programmers have different methods to invert this pin. ce when high, this pin disables the internal address counter, 3-states the data output, and forces the device into low-i cc standby mode. ceo chip enable output, to be connected to the ce input of the next prom in the daisy chain. this output is low when the ce and oe inputs are both active and the internal address counter has been incremented beyond its terminal count (tc) value. in other words: when the prom has been read, ceo will follow ce as long as oe is active. when oe goes inactive, ceo stays high until the prom is reset. note: oe can be programmed to be either active high or active low. v pp programming voltage. no overshoot above the specified maximum voltage is permitted on this pin. for normal read operation, this pin must be connected to v cc . failure to do so can lead to unpredictable, temperature-dependent operation and severe problems. do not leave v pp floating! v cc and gnd v cc is positive supply pin and gnd is ground pin.
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 3 prom pinouts capacity number of configuration bits, including he ader, for xilinx fpgas and compatible proms controlling proms connecting the fpga device with the prom. ? the data output(s) of the prom(s) drives the d in input of the lead fpga device. ? the master fpga cclk output drives the clk input(s) of the prom(s). ?the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the reset /oe input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any reconfiguration, even when a reconfiguration is initiated by a v cc glitch. other methods?such as driving reset /oe from ldc or system reset?assu me the prom internal power-on-reset is always in step with the fpga?s internal power-on-reset. this might not be a safe assumption. ?the prom ce input can be driven from either the ldc or done pins. using ldc avoids potential contention on the d in pin. ?the ce input of the lead (or only) prom is driven by the done output of the lead fpga device, provided that done is not permanently grounded. otherwise, ldc can be used to drive ce , but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. ta bl e 1 : prom pinouts pin name pin number data 1 clk 2 reset/oe (oe/reset )3 ce 4 gnd 5 ceo 6 v pp 7 v cc 8 ta bl e 2 : capacity devices configuration bits xc1765e 65,536 xc17256e 262,144 ta bl e 3 : number of configuration bits, including header, for xilinx fpgas and compatible proms device configuration bits prom XC3000/a series 14,819 to 94,984 xc1765e to xc17256e xc4000 series 95,008 to 247,968 xc17256e xq4005e 95,008 xc17256e xq4010e 178,144 xc17256e xq4013e 247,968 xc17256e
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 4 fpga master serial mode summary the i/o and logic functions of the configurable logic block (c lb) and their associated interconnections are established by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the configuration program from an external memory. the xilinx proms have been design ed for compatibility with th e master serial mode. upon power-up or reconfiguration, an fpga enters the master serial mode whenever all three of the fpga mode-select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. synchronization is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration interface. only a serial data line and two control lines are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function d in pin on the fpga is used on ly for configuration, it must still be held at a defined level during normal operation. xilinx fp gas take care of this automatically with an on-chip default pull-up resistor. programming the fpga with coun ters unchanged upon completion when multiple fpga-configurations for a single fpga are stored in a prom, the oe pin should be tied low. upon power-up, the internal address counters are reset and config uration begins with the first program stored in memory. since the oe pin is held low, the address counters are left unchanged after configuration is complete. therefore, to reprogram the fpga with another program, the done line is pulled low and configuration begins at the last value of the address counters. this method fails if a user applies reset during the fpga configuration process. the fpga aborts the configuration and then restarts a new configuration, as intended, but the prom does not reset its address counter, since it never saw a high level on its oe input. the new configuration, therefore, reads the remaining data in the prom and interprets it as preamble, length count etc. since the fpga is the master, it issues the necessary number of cclk pulses, up to 16 million (2 24 ) and done goes high. however, the fpga conf iguration will be completely wrong, with potential contentions inside the fpga and on its output pins. this method must, therefore, never be used when there is any chance of external reset during configuration. cascading configuration proms for multiple fpgas configured as a daisy-chain, or for future fpgas requiring larger configuration memories, cascaded proms provide additional memory. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and disables its data line. the second prom recognizes the low level on its ce input and enables its data output. see figure 2 . after configuration is complete, the address counters of all cascaded proms are reset if the fpga reset pin goes low, assuming the prom reset polarity option has been inverted. to reprogram the fpga with another program, the done line goes low and configuration begins where the address counters had stopped. in this case, avoid contention between data and the configured i/o use of d in .
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 5 x-ref target - figure 2 figure 2: master serial mode d in d out cclk init done prom data clk ce ce fpga v cc v cc v cc optional d a i s y-ch a ined fpga s with different config u r a tion s optional s l a ve fpga s with identic a l config u r a tion s re s et re s et d s 670_02_120210 cclk (o u tp u t) d in d out (o u tp u t) oe/re s et mode s (1) v pp c as c a ded s eri a l memory data clk ceo oe/re s et 3 . 3 v 4.7k note s : 1. for mode pin connection s , refer to the a ppropri a te fpga d a t a s heet. 2. the one-time-progr a mm ab le prom su pport s au tom a tic lo a ding of config u r a tion progr a m s . 3 . m u ltiple device s c a n b e c as c a ded to su pport a ddition a l fpga s . 4. an e a rly done inhi b it s the prom d a t a o u tp u t one cclk cycle b efore the fpga i/o s b ecome a ctive.
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 6 standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high impedance state regardless of the state of the oe input. programming the devices can be programmed on progra mmers supplied by xilinx or qualified third- party vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. note: always tie the v pp pin to v cc in your application. never leave v pp floating. ta bl e 4 : truth table for xc1700 control inputs control inputs internal address outputs reset (1) ce data ceo i cc inactive low if address ? tc: increment if address > tc: don?t change (2) active high-z high low active reduced active low held reset high-z high active inactive high not changing high-z (3) high standby active high held reset high-z (3) high standby notes: 1. the xc1700 reset input has programmable polarity 2. tc = terminal count = highest address value with valid data. 3. pull data pin to gnd or v cc to meet i ccs standby current.
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 7 xc1765e and xc17256e absolute maximum ratings operating conditions dc characteristics over operating condition ta bl e 5 : absolute maximum ratings symbol description range units v cc supply voltage relative to gnd ?0.5 to +7.0 v v pp supply voltage relative to gnd ?0.5 to +12.5 v v in input voltage relative to gnd ?0.5 to v cc +0.5 v v ts voltage applied to high-z output ?0.5 to v cc +0.5 v t stg storage temperature (ambient) ?65 to +150 c t j junction temperature (10s @ 1/16 in.) +125 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. ta bl e 6 : operating conditions symbol description min max units v cc (1) supply voltage relative to gnd (t c = ?55c to +125c) 4.50 5.50 v notes: 1. during normal read operation v pp must be connected to v cc ta bl e 7 : dc characteristics over operating condition symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ?4 ma) 3.7 ? v v ol low-level output voltage (i ol = +4 ma) ? 0.4 v i cca supply current, active mode (at maximum frequency) ? 10 ma i ccs supply current, standby mode xc17256e ? 50 (1) a xc1765e ? 1.5 (1) ma i l input or output leakage current ?10 10 a c in input capacitance (v in = gnd, f = 1.0 mhz) sample tested ? 10 pf c out output capacitance (v in = gnd, f = 1.0 mhz) sample tested ? 10 pf notes: 1. i ccs standby current is specified for data pin that is pulled to v cc or gnd.
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 8 ac characteristics over operating condition x-ref target - figure 3 figure 3: ac characteristics ov er operating condition ta bl e 8 : ac characteristics over operating condition (1)(2) symbol description xc1765e xc17256e units min max min max t oe oe to data delay ? 45 ? 25 ns t ce ce to data delay ? 60 ? 45 ns t cac clk to data delay ? 150 ? 50 ns t oh data hold from ce , oe , or clk (3) 0?0 ?ns t df ce or oe to data float delay (3)(4) ?50?50ns t cyc clock periods 200 ? 80 ? ns t lc clk low time (3) 100 ? 20 ? ns t hc clk high time (3) 100 ? 20 ? ns t sce ce setup time to clk (to guarantee proper counting) 25 ? 20 ? ns t hce ce hold time to clk (to guarantee proper counting) 0 ? 0 ? ns t hoe oe hold time (guarantees counters are reset) 100 ? 20 ? ns notes: 1. ac test load = 50 pf 2. all ac parameters are measured with v i l = 0.0v and v ih = 3.0v. 3. guaranteed by design, not tested. 4. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds070_03_111010 t cyc
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 9 ac characteristics over operating condition when cascading x-ref target - figure 4 figure 4: ac characteristics over operating condition when cascading ta bl e 9 : ac characteristics over operating condition when cascading (1)(2) symbol description xc1765e xc17256e units min max min max t cdf clk to data float delay (3)(4) ?50?50ns t ock clk to ceo delay (3) ?65?30ns t oce ce to ceo delay (3) ?45?35ns t ooe reset/oe to ceo delay (3) ?40?30ns notes: 1. ac test load = 50 pf 2. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 3. guaranteed by design, not tested. 4. float delays are measured with 5 pf ac loads. transition is measured at 200mv from steady state active levels. re s et/oe clk data (fir s t prom) data (c as c a ded prom) ce ceo (fir s t prom) ce (c as c a ded prom) l as t bit l as t bit fir s t bit fir s t bit d s 670_04_120210 n nn +1 n ?1 t cdf t ooe t ock t oce t oce t ce t ce
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 10 ordering information valid ordering combinations marking information due to the small size of the prom package, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. devices are marked as shown in figure 6 . revision history the following table shows the revision history for this document. x-ref target - figure 5 figure 5: ordering information ta bl e 1 0 : valid ordering combinations xc17256edd8m xc1765edd8m xc17256edd8b xc1765edd8b x-ref target - figure 6 figure 6: marking information date version revisions 12/03/10 1.0 initial xilinx release. xc17256e dd 8 m oper a ting r a nge/proce ss ing m = milit a ry (t c = ?55 to +125c) b = milit a ry (t c = ?55 to +125c) p a ck a ge type dd 8 = 8 -pin cer a mic dip device n u m b er xc1765e xc17256e d s 670_05_120210 17256e d m oper a ting r a nge/proce ss ing m = milit a ry (t c = ?55 to +125c) b = milit a ry (t c = ?55 to +125c) p a ck a ge type d = 8 -pin cer a mic dip device n u m b er xc1765e xc17256e d s 670_06_120 3 10
qpro family of xc1700e configuration proms ds670 (v1.0) december 3, 2010 www.xilinx.com product specification 11 notice of disclaimer the xilinx hardware devices referred to herein (?pro ducts?) are subject to the terms and conditions of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fa il-safe performance, such as life-support or safety devices or systems, or any other application that invokes the potential risks of death, personal injury, or property or envi ronmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. critical applications disclaimer xilinx products (including hardware, software and/or ip cores) are not designed or intended to be fail-safe, or for use in any applic ation requiring fail-safe performance, such as in life-support or safety devices or systems, class iii medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications th at could lead to death, personal injury or severe property or environmental damage (individually and collectively, ?critical appl ications?). furthermore, xilinx products are not designed or intended for use in any applications that affect control of a vehicle or aircraft, unless there is a fail-safe or redundancy feature (which does not include use of software in the xilinx device to implement the re dundancy) and a warning signal upon failure to the operator. customer agrees, prior to using or dist ributing any systems that incorporate xilinx products, to thoroughly test the same for safet y purposes. to the maximum extent permitted by applicable law, customer assumes the sole risk and liabi lity of any use of xili nx products in critical applications.

▲Up To Search▲

Price & Availability of XC3000

	To Download XC3000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .